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Preliminary GS816018/32/36T-225/200/180/166/150/133 100-Pin TQFP Commercial Temp Industrial Temp Features
* FT pin for user-configurable flow through or pipeline operation * Single Cycle Deselect (SCD) operation * 2.5 V +10%/-5% core power supply * 2.5 V or 3.3 V I/O supply * LBO pin for Linear or Interleaved Burst mode * Internal input resistors on mode pins allow floating mode pins * Default to Interleaved Pipeline mode * Byte Write (BW) and/or Global Write (GW) operation * Internal self-timed write cycle * Automatic power-down for portable applications * JEDEC-standard 100-lead TQFP package -225 2.5 Pipeline tKQ 4.4 3-1-1-1 tCycle Curr (x18) 350 Curr (x32) 410 Curr (x36) 410 7.0 Flow tKQ 8.5 Through tCycle 2-1-1-1 Curr (x18) 205 Curr (x32) 240 Curr (x36) 240 -200 3.0 5.0 315 370 370 7.5 10 185 210 210 -180 3.2 5.5 290 340 340 8 10 185 210 210 -166 3.5 6.0 270 315 315 8.5 10 185 210 210 -150 3.8 6.6 250 290 290 -133 4.0 7.5 230 260 260 Unit ns ns mA mA mA ns ns mA mA mA
1M x 18, 512K x 32, 512K x 36 16Mb Sync Burst SRAMs
225 MHz-133 MHz 2.5 V VDD 2.5 V or 3.3 V I/O
counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.
SCD Pipelined Reads
The GS816018/32/36T is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
10 11 10 15 185 140 210 160 210 160
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Functional Description
Applications
The GS816018/32/36T is a 18,874,368-bit (16,777,216-bit for x32 version) high performance synchronous SRAM with a 2bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM application,s ranging from DSP main store to networking chip set support.
Core and Interface Voltages
The GS816018/32/36T operates on a 2.5 V power supply. All input are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V- and 2.5 V-compatible.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address Rev: 2.08 11/2000 1/26 (c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133
GS816018 100-Pin TQFP Pinout
NC NC NC VDDQ VSS NC NC DQB1 DQB2 VSS VDDQ DQB3 DQB4 FT VDD NC VSS DQB5 DQB6 VDDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9
A19 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC
Rev: 2.08 11/2000
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A3 A2 A1 A0 NC NC VSS VDD A18 A17 A10 A11 A12 A13 A14 A15 A16 2/26 (c) 1999, Giga Semiconductor, Inc.
Preliminary GS816018/32/36T-225/200/180/166/150/133
GS816032 100-Pin TQFP Pinout
NC DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9
NC DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 NC
Rev: 2.08 11/2000
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A3 A2 A1 A0 NC NC VSS VDD A18 A17 A10 A11 A12 A13 A14 A15 A16 3/26 (c) 1999, Giga Semiconductor, Inc.
Preliminary GS816018/32/36T-225/200/180/166/150/133
GS816036 100-Pin TQFP Pinout
DQC9 DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 DQD9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9
DQB9 DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 DQA9
Rev: 2.08 11/2000
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A3 A2 A1 A0 NC NC VSS VDD A18 A17 A10 A11 A12 A13 A14 A15 A16 4/26 (c) 1999, Giga Semiconductor, Inc.
Preliminary GS816018/32/36T-225/200/180/166/150/133
TQFP Pin Description Pin Location
37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43, 42, 80 63, 62, 59, 58, 57, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 13, 12, 9, 8, 7, 6, 3, 2 18, 19, 22, 23, 24, 25, 28, 29 51, 80, 1, 30 51, 80, 1, 30 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 51, 52, 53, 56, 57 75, 78, 79, 1, 2, 3, 6, 7, 25, 28, 29, 30 87 93, 94 95, 96 95, 96 89 88 98, 92 97 86 83 84, 85 64 14 31 15, 41, 65, 91 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77 16, 38, 39, 66
Symbol
A0, A1 A2-A18 A19 DQA1-DQA8 DQB1-DQB8 DQC1-DQC8 DQD1-DQD8 DQA9, DQB9, DQC9, DQD9 NC DQA1-DQA9 DQB1-DQB9 NC BW BA, BB BC, BD NC CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS VDDQ NC
Typ e
I I I I/O
Description
Address field LSBs and Address Counter preset Inputs Address Inputs Address Inputs (x18 versions) Data Input and Output pins (x32, x36 Version)
I/O
Data Input and Output pins (x36 Version) No Connect (x32 Version)
I/O
Data Input and Output pins (x18 Version)
-- I I I -- I I I I I I I I I I I I I --
No Connect (x18 Version) Byte Write--Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/Os; active low Byte Write Enable for DQC, DQD Data I/Os; active low (x32, x36 Version) No Connect (x18 Version) Clock Input Signal; active high Global Write Enable--Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply No Connect
Rev: 2.08 11/2000
5/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133
GS816018/32/36 Block Diagram
Register
A0-An
D
Q A0 D0 A1 D1 Q1 Counter Load A Q0 A0 A1
LBO ADV CK ADSC ADSP GW BW BA
Register
Memory Array
Q D Q D
Register
D BB
Q
36 4
36
Register
D BC
Q Q
Register
D
Register
Q
Register
D
D BD
Q
Register
D
Q
Register
E1 E2 E3
D
Q
Register
D
Q
FT G Power Down Control
1
ZZ
DQx0-DQx9
Note: Only x36 version shown for simplicity.
Rev: 2.08 11/2000
6/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133
Mode Pin Functions Mode Name
Burst Order Control Output Register Control Power Down Control
Pin Name
LBO FT ZZ
State
L H L H or NC L or NC H
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB
Note: There is a pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 2.08 11/2000
7/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133
Byte Write Truth Table Function
Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes Write all bytes
GW
H H H H H H H L
BW
H L L L L L L X
BA
X H L H H H L X
BB
X H H L H H L X
BC
X H H H L H L X
BD
X H H H H L L X
Notes
1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4
Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes "C" and "D" are only available on the x32 and x36 versions.
Rev: 2.08 11/2000
8/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133
Synchronous Truth Table Operation
Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
Address Used
None None None External External External Next Next Next Next Current Current Current Current
State Diagram Key5
X X X R R W CR CR CW CW
E1
H L L L L L X H X H X H X H
E2
X F F T T T X X X X X X X X
ADSP ADSC
X L H L H H H X H X H X H X L X L X L L H H H H H H H H
ADV
X X X X X X L L L L H H H H
W3
X X X X F T F F T T F F T T
DQ4
High-Z High-Z High-Z Q Q D Q Q D D Q Q D D
Notes: 1. X = Don't Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as "Q" in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 2.08 11/2000
9/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133 Simplified State Diagram
X
Deselect W W Simple Synchronous Operation R R
X CW
First Write
R CR
First Read
X CR
Simple Burst Synchronous Operation
W R X Burst Write CR CW
R
Burst Read
X
CR
Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low.
Rev: 2.08 11/2000
10/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133 Simplified State Diagram with G
X
Deselect W W X W CW R R
First Write
R CR
First Read
X CR
CW
W X Burst Write R CR W CW
R X
Burst Read
CW
CR
Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet Data Input Set Up Time.
Rev: 2.08 11/2000
11/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VCK VI/O VIN IIN IOUT PD TSTG TBIAS
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage on Clock Input Pin Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 to 3.6 -0.5 to 3.6 -0.5 to 6 -0.5 to VDDQ+0.5 ( 3.6 V max.) -0.5 to 3.6 +/-20 +/-20 1.5 -55 to 125 -55 to 125
Unit
V V V V V mA mA W
oC oC
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Recommended Operating Conditions Parameter
Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
VDD VDDQ VIH VIL TA TA
Min.
2.375 2.375 0.7 * VDD -0.3 0 -40
Typ.
2.5 2.5 -- -- 25 25
Max.
2.7 3.6 3.6 0.3 * VDD 70 85
Unit
V V V V C C
Notes
1 1 2 2
Note: 1. The part number of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDD+2 V with a pulse width not to exceed 20% tKC.
Rev: 2.08 11/2000
12/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133
Undershoot Measurement and Timing
VIH VDD + 2.0 V VSS 50% VSS - 2.0 V 20% tKC VIL 50% VDD
Overshoot Measurement and Timing
20% tKC
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters are sample tested.
Symbol
CIN CI/O
Test conditions
VIN = 0 V VOUT = 0 V
Typ.
4 6
Max.
5 7
Unit
pF pF
Package Thermal Characteristics Rating
Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP)
Layer Board
single four --
Symbol
RJA RJA RJC
Max
40 24 9
Unit
C/W C/W C/W
Notes
1,2 1,2 3
Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 2.08 11/2000
13/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133
AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level Output load
Conditions
2.3 V 0.2 V 1 V/ns 1.25 V 1.25 V Fig. 1& 2
Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ 4. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50 VT = 1.25 V
* Distributed Test Jig Capacitance
Output Load 2 2.5 V 30pF* DQ 5pF* 225 225
DC Electrical Characteristics Parameter
Input Leakage Current (except mode pins) ZZ Input Current Mode Pin Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage
Symbol
IIL IINZZ IINM IOL VOH VOH VOL
Test Conditions
VIN = 0 to VDD VDD VIN VIH 0 V VIN VIH VDD VIN VIL 0 V VIN VIL Output Disable, VOUT = 0 to VDD IOH = -8 mA, VDDQ = 2.375 V IOH = -8 mA, VDDQ = 3.135 V IOL = 8 mA
Min
-1 uA -1 uA -1 uA -300 uA -1 uA -1 uA 1.7 V 2.4 V --
Max
1 uA 1 uA 300 uA 1 uA 1 uA 1 uA -- -- 0.4 V
Rev: 2.08 11/2000
14/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Operating Currents
-225 Mode IDD IDDQ IDD IDDQ IDD IDDQ 310 37 186 19 10 10 80 60 65 50 55 50 85 75 80 70 75 55 20 10 20 10 20 10 64 50 20 10 20 10 20 10 20 20 70 55 196 29 166 17 176 27 166 17 176 27 166 17 176 27 166 17 10 10 60 50 320 47 281 33 291 43 258 30 268 40 242 27 252 37 223 25 IDD IDDQ ISB ISB IDD IDD 233 35 176 27 20 20 65 55 199 39 209 49 177 33 187 43 177 33 187 43 177 33 187 43 177 33 187 43 134 22 204 22 127 11 10 10 50 45 335 74 345 84 303 66 313 76 278 59 288 69 260 55 270 65 240 50 250 60 218 44 Symbol 0 to 70C -40 to 85C Unit
228 54 144 32 214 32 137 21 20 20 55 50 mA mA mA mA mA mA mA mA
-200 0 to 70C -40 to 85C -40 to 85C -40 to 85C -40 to 85C -40 to 85C 0 to 70C 0 to 70C 0 to 70C 0 to 70C
-180
-166
-150
-133
Rev: 2.08 11/2000 Pipeline (x36) Flow Through Pipeline (x18) Flow Through Pipeline -- Flow Through Pipeline -- Flow Through
Parameter
Test Conditions
Operating Current
Device Selected; All other inputs VIH or VIL Output open
Standby Current
ZZ VDD - 0.2 V
15/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Deselect Current
Device Deselected; All other inputs VIH or VIL
Preliminary GS816018/32/36T-225/200/180/166/150/133
(c) 1999, Giga Semiconductor, Inc.
Preliminary GS816018/32/36T-225/200/180/166/150/133 AC Electrical Characteristics
Parameter Clock Cycle Time Pipeline Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Flow Through Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z Setup time Hold time ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ
1
-225 Min 4.4 -- 1.5 1.5 8.5 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 100 Max -- 2.5 -- -- -- 7.0 -- -- -- -- 2.5 2.5 -- 2.5 -- -- -- -- --
-200 Min 5.0 -- 1.5 1.5 10.0 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 100 Max -- 3.0 -- -- -- 7.5 -- -- -- -- 3.0 3.2 -- 3.0 -- -- -- -- --
-180 Min 5.5 -- 1.5 1.5 10.0 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 100 Max -- 3.2 -- -- -- 8.0 -- -- -- -- 3.2 3.2 -- 3.2 -- -- -- -- --
-166 Min 6.0 -- 1.5 1.5 10.0 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 100 Max -- 3.5 -- -- -- 8.5 -- -- -- -- 3.5 3.5 -- 3.5 -- -- -- -- --
-150 Min 6.7 -- 1.5 1.5 10.0 -- 3.0 3.0 1.5 1.7 1.5 -- 0 -- 1.5 0.5 5 1 100 Max -- 3.8 -- -- -- 10.0 -- -- -- -- 3.8 3.8 -- 3.8 -- -- -- -- --
-133 Min 7.5 -- 1.5 1.5 15.0 -- 3.0 3.0 1.7 2 1.5 -- 0 -- 1.5 0.5 5 1 100 Max -- 4.0 -- -- -- 11.0 -- -- -- -- 4.0 4.0 -- 4.0 -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tKC tKQ tKQX tLZ1 tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tS tH tZZS2 tZZH2 tZZR
Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.
Rev: 2.08 11/2000
16/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133 Write Cycle Timing
Single Write
Burst Write
Write
Deselected
CK
tS tH
tKH tKL
tKC
ADSP is blocked by E inactive
ADSP
tS tH ADSC initiated write
ADSC
tS tH
ADV
tS tH ADV must be inactive for ADSP Write
WR2 WR3
A0-An GW
WR1
tS tH
tS tH
BW
tS tH
BA-BD
tS tH
WR1 WR1
WR2
WR3 WR3
E1 masks ADSP
E1
tS tH Deselected with E2
E2
tS tH E2 and E3 only sampled with ADSP or ADSC
E3 G
tS tH Write specified byte for 2A and all bytes for 2B, 2C& 2D
D2A D2B D2C D2D D3A
DQA-DQD
Hi-Z
D1A
Rev: 2.08 11/2000
17/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133 Flow Through Read Cycle Timing
Single Read tKL
Burst Read
CK
tS tH tKH tKC ADSP is blocked by E inactive
ADSP
tS tH ADSC initiated read
ADSC
tS tH Suspend Burst Suspend Burst
ADV
tS tH
A0-An GW
RD1 tS
RD2
RD3 tH
tS
tH
BW BA-BB
tS tH E1 masks ADSP
E1
tS tH E2 and E3 only sampled with ADSP or ADSC Deselected with E2
E2
tS tH
E3
tOE tOHZ
G
tOLZ tKQX Q1A tLZ tKQ tHZ Q2A Q2B Q2c Q2D Q3A tKQX
DQA-DQD
Hi-Z
Rev: 2.08 11/2000
18/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133 Flow Through Read-Write Cycle Timing
Single Read Single Write
Burst Read
CK
tS tH tKH tKL tKC ADSP is blocked by E inactive
ADSP
tS tH ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0-An GW
RD1
WR1
RD2
tS tH
tS
tS tH
BW BA-BD
tS tH tS
WR1
tH
E1 masks ADSP
E1
tS tH E2 and E3 only sampled with ADSP and ADSC
E2
tS tH Deselected with E3 tOHZ
E3
tOE
G
tKQ tS Q1A tH Q2A Q2B Q2c Q2D Q2A
DQA-DQD
Hi-Z
D1A
Burst wrap around to it's initial state
Rev: 2.08 11/2000
19/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133 Pipelined SCD Read Cycle Timing
Single Read Burst Read tKH tKL tKC tS tH ADSC initiated read ADSP is blocked by E inactive
CK
tS tH
ADSP ADSC
tS tH
Suspend Burst
ADV
tS tH
A0-An GW
RD1 tS
RD2
RD3 tH
tS
tH
BW BWA-BWD
tS tH E1 masks ADSP
E1
tS tH E2 and E3 only sampled with ADSP or ADSC Deselected with E2
E2
tS tH
E3
tOE
G DQA-DQD
Hi-Z tOLZ Q1A tLZ
tOHZ tKQX Q2A Q2B Q2c Q2D
tKQX Q3A tHZ
tKQ
Rev: 2.08 11/2000
20/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133 Pipelined SCD Read-Write Cycle Timing
Single Read tKL Single Write Burst Read
CK
tS tH tKH tKC tS tH ADSP is blocked by E inactive
ADSP
ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0-An GW
RD1
WR1
RD2
tS tH
tS
tH
BW
tS tH
BWA-BWD
tS tH
WR1
E1 masks ADSP
E1
tS tH E2 and E3 only sampled with ADSP and ADSC
E2
tS tH Deselected with E3
E3
tOE tOHZ
G DQA-DQD
Hi-Z tKQ Q1A tS tH D1A Q2A Q2Bb Q2c Q2D
Rev: 2.08 11/2000
21/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133 Sleep Mode Timing Diagram
CK
tS tH tKC tKH tKL
ADSP ADSC
tZZS
~ ~~~~ ~ ~~~~ ~
tZZH
tZZR
ZZ
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of "dummy read cycles" (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.
Rev: 2.08 11/2000
22/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133 TQFP Package Drawing
L Symbol
A1 A2 b c D D1 E E1 e L L1 Y
c Pin 1
Description
Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle
Min. Nom. Max
0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 -- 0.45 -- 0.10 1.40 0.30 -- 22.0 20.0 16.0 14.0 0.65 0.60 1.00 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 -- 0.75 -- 0.10
L1
D D1
e b
A1
Y
A2
0
--
7
E1 E
Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion.
Rev: 2.08 11/2000
23/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133 Ordering Information for GSI Synchronous Burst RAMs
Org
1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32
Part Number1
GS816018T-225 GS816018T-200 GS816018T-180 GS816018T-166 GS816018T-150 GS816018T-133 GS816032T-225 GS816032T-200 GS816032T-180 GS816032T-166 GS816032T-150 GS816032T-133 GS816036T-225 GS816036T-200 GS816036T-180 GS816036T-166 GS816036T-150 GS816036T-133 GS816018T-225I GS816018T-200I GS816018T-180I GS816018T-166I GS816018T-150I GS816018T-133I GS816032T-225I GS816032T-200I GS816032T-180I GS816032T-166I GS816032T-150I GS816032T-133I
Type
Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through
Package
TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP
Speed2 (MHz/ns)
225/7 200/7.5 180/8 166/8.5 150/10 133/11 225/7 200/7.5 180/8 166/8.5 150/10 133/11 225/7 200/7.5 180/8 166/8.5 150/10 133/11 225/7 200/7.5 180/8 166/8.5 150/10 133/11 225/7 200/7.5 180/8 166/8.5 150/10 133/11
TA3
C C C C C C C C C C C C C C C C C C I I I I I I I I I I I I
Status
Not Available Not Available
Not Available Not Available
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816018T-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 2.08 11/2000 24/26 (c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133
Org
512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36
Part Number1
GS816036T-225I GS816036T-200I GS816036T-180I GS816036T-166I GS816036T-150I GS816036T-133I
Type
Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through
Package
TQFP TQFP TQFP TQFP TQFP TQFP
Speed2 (MHz/ns)
225/7 200/7.5 180/8 166/8.5 150/10 133/11
TA3
I I I I I I
Status
Not Available Not Available
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816018T-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 2.08 11/2000
25/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816018/32/36T-225/200/180/166/150/133
0.18u 16M Sync SRAM Data Sheet Revision History DS/DateRev. Code: Old; New
GS816018T-150IT 1.00 9/ 1999A;GS816018T-150IT 2.00 1/1999B GS816018T- 2.00 11/ 1999B;GS816018T 2.01 1/ 2000C GS816018T 2.01 1/ 2000C;GS816018 T 2.02 1/ 2000D
Types of Changes Format or Content
Content
Page;Revisions;Reason
* Converted from 0.25u 3.3V process to 0.18u 2.5V process. Master File Rev B * Added x72 Pinout. * Added GSI Logo. * Changed Flow-Through Read-Write cycle Timing Diagram for accuracy * Changed pin description in TQFP to match order of pins in pinout. * Front page; Features - changed 2.5V I/O supply to 2.5V or3.3V I/O supply; Core and Interface voltages - Changed paragraph to include information for 3.3V;Completeness * Absolute Maximum Ratings; Changed VDDQ - Value: From: .05 to VDD : to : -.05 to 3.6; Completeness. * Recommended Operating Conditions;Changed: I/O Supply Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from VDD +0.3 to 3.6; Same page - took out Note 1;Completeness * Electrical Characteristics - Added second Output High Voltage line to table; completeness. * Note: There was not a Rev 2.02 for the 8160Z or the 8161Z.
Format
GS18/362.0 1/2000DGS18/ 362.03 2/2000E
GS18/362.03 2/2000E; 816018_r2_04 816018_r2_04; 816018_r2_05
Content Content
* Input High Voltage (p. 11) changed to 0.7* VDD * Input Low Voltage (p.11) changed to 0.3* VDD * Changed the value of ZZ recovery in the AC Electrical Characteristics table on page 15 from 20 ns to 100 ns * Added 225 MHz speed bin * Updated Pg. 1 table, AC Characteristics table, and Operating Currents table to match 815xxx * Updated format to comply with Technical Publications standards * Updated Capitance table--removed Input row and changed Output row to I/O * Updated Features list on page 1 * Completely reworked table on page 1 * Updated Mode Pin Functions tableon page 7
816018_r2_05; 816018_r2_06
Content/Format
816018_r2_06; 816018_r2_07 816018_r2_07; 816018_r2_08
Content
Content
Rev: 2.08 11/2000
26/26
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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